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ds310 (v1.1) august 30, 2004 www.xilinx.com 1 advance product specification 1-800-255-7778 ? 2003 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? optimized for 1.8v systems - as fast as 3.0 ns pin-to-pin logic delays - as low as 12 a quiescent current ? industry?s best 0.18 micron cmos cpld - optimized architecture for effective logic synthesis - multi-voltage i/o operation: 1.5v through 3.3v ? available in multiple package options - 32-land qfn with 21 user i/o - 44-pin plcc with 33 user i/o - 44-pin vqfp with 33 user i/o - 56-ball cp bga with 33 user i/o - pb-free available for all packages ? advanced system features - fastest in system programming 1.8v isp using ieee 1532 (jtag) interface - ieee1149.1 jtag boundary scan test - optional schmitt-trigger input (per pin) - i/o banking - realdigital 100% cmos product term generation - flexible clocking modes - optional dualedge triggered registers - global signal options with macrocell control multiple global clocks with phase selection per macrocell multiple global output enables global set/reset - efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks - advanced design security - open-drain output option for wired-or and led drive - optional configurable grounds on unused i/os - optional bus-hold, 3-state or weak pullup on selected i/o pins - mixed i/o voltages compatible with 1.5v, 1.8v, 2.5v, and 3.3v logic levels - pla architecture superior pinout retention 100% product term routability across function block - hot pluggable refer to the coolrunner?-ii family data sheet for architec- ture description. description the coolrunner-ii 32-macrocell device is designed for both high performance and low power applications. this lends power savings to high-end communication equipment and high speed to battery operated devices. due to the low power stand-by and dynamic operation, overall system reli- ability is improved this device consists of two function blocks interconnected by a low power advanced interconnect matrix (aim). the aim feeds 40 true and complement inputs to each function block. the function blocks consist of a 40 by 56 p-term pla and 16 macrocells which contain numerous configura- tion bits that allow for combinational or registered modes of operation. additionally, these registers can be globally reset or preset and configured as a d or t flip-flop or as a d latch. there are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. a schmitt trigger input is available on a per input pin basis. in addition to stor- ing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. clocking is available on a global or function block basis. three global clocks are available for all function blocks as a synchronous clock source. macrocell registers can be individually configured to power up to the zero or one state. a global set/reset control line is also available to asynchro- nously set or reset selected registers during operation. additional local clock, synchronous clock-enable, asynchro- nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-function block basis. the coolrunner-ii 32-macrocell cpld is i/o compatible with standard lvttl and lvcmos18, lvcmos25, and lvcmos33 (see ta b le 1 ). this device is also 1.5v i/o com- patible with the use of schmitt-trigger inputs. 0 xc2c32a coolrunner-ii cpld ds310 (v1.1) august 30, 2004 00 advance product specification r
xc2c32a coolrunner-ii cpld 2 www.xilinx.com ds310 (v1.1) august 30, 2004 1-800-255-7778 advance product specification r realdigital design technology xilinx coolrunner-ii cplds are fabricated on a 0.18 micron process technology which is derived from leading edge fpga product development. coolrunner-ii cplds employ realdigital, a design technique that makes use of cmos technology in both the fabrication and design methodology. realdigital design technology employs a cascade of cmos gates to implement sum of products instead of traditional sense amplifier methodology. due to this technology, xilinx coolrunner-ii cplds achieve both high performance and low power operation. supported i/o standards the coolrunner-ii 32 macrocell features both lvcmos and lvttl i/o implementations. see ta b l e 1 for i/o stan- dard voltages. the lvttl i/o standard is a general purpose eia/jedec standard for 3.3v applications that use an lvttl input buffer and push-pull output buffer. the lvcmos standard is used in 3.3v, 2.5v, 1.8v applications. coolrunner-ii cplds are also 1.5v i/o compatible with the use of schmitt-trigger inputs. table 1: i/o standards for xc2c32a i/o types output v ccio input v ccio input v ref board terminatio nvoltage v t lvttl 3.3 3.3 n/a n/a lvcmos33 3.3 3.3 n/a n/a lvcmos25 2.5 2.5 n/a n/a lvcmos18 1.8 1.8 n/a n/a 1.5v i/o 1.5 1.5 n/a n/a figure 1: i cc vs frequency table 2: i cc vs frequency (lvcmos 1.8v t a = 25c) (1) frequency (mhz) 0 25 50 75 100 150 175 200 225 250 300 350 385 typical -3 i cc (ma) 0.03 0.98 1.92 2.90 3.82 5.68 6.65 7.54 8.41 9.35 11.16 12.97 14.09 typical -4, -6 i cc (ma) 0.016 0.87 1.75 2.61 3.44 5.16 5.99 6.81 7.63 8.36 9.93 - - notes: 1. 16-bit up/down, resettable binary counter (one counter per function block). frequency (mhz) ds091_01_042303 i cc (ma) 0 0 5 10 15 20 300 250 200 150 100 50 350 -4, -6 -3 400
xc2c32a coolrunner-ii cpld ds310 (v1.1) august 30, 2004 www.xilinx.com 3 advance product specification 1-800-255-7778 r recommended operating conditions dc electrical characteristics (over recommended operating conditions) absolute maximum ratings symbol description value units v cc supply voltage relative to ground ?0.5 to 2.0 v v ccio supply voltage for output drivers ?0.5 to 4.0 v v jtag (2) jtag input voltage limits ?0.5 to 4.0 v v aux jtag input supply voltage ?0.5 to 4.0 v v in (1) input voltage relative to ground ?0.5 to 4.0 v v ts (1) voltage applied to 3-state output ?0.5 to 4.0 v t stg (3) storage temperature (ambient) ?65 to +150 c t j junction temperature +150 c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easiest to achieve. during transitions, the device pins may undershoot to ?2.0v or overshoot to +4.5v, provided this over or undershoot lasts less than 10 ns and with t he forcing current being limited to 200 ma. 2. valid over commercial temperature range. 3. for soldering guidelines and thermal considerations, see the device packaging information on the xilinx website. for pb free packages, see xapp427 . symbol parameter min max units v cc supply voltage for internal logic and input buffers commercial t a = 0c to +70c 1.7 1.9 v industrial t a = ?40c to +85c 1.7 1.9 v v ccio supply voltage for output drivers @ 3.3v operation 3.0 3.6 v supply voltage for output drivers @ 2.5v operation 2.3 2.7 v supply voltage for output drivers @ 1.8v operation 1.7 1.9 v supply voltage for output drivers @ 1.5v operation 1.4 1.6 v v aux jtag programming pins 1.7 3.6 v symbol parameter test conditions typical max. units i ccsb standby current (-3) v cc = 1.9v, v ccio = 3.6v 150 1000 a i ccsb standby current (-4, -6) v cc = 1.9v, v ccio = 3.6v 22 50 a i ccsb standby current ( -6 industrial) v cc = 1.9v, v ccio = 3.6v 38 80 a i cc (1) dynamic current (-3) f = 1 mhz - 1.2 ma f = 50 mhz - 4.0 ma i cc (1) dynamic current (-4, -6) f = 1 mhz - 0.25 ma f = 50 mhz - 2.5 ma c jtag jtag input capacitance f = 1 mhz - 10 pf c clk global clock input capacitance f = 1 mhz - 12 pf c io i/o capacitance f = 1 mhz - 10 pf i il (2) input leakage current v in = 0v or v ccio to 3.9v ?1 1 a i ih (2) i/o high-z leakage v in = 0v or v ccio to 3.9v ?1 1 a notes: 1. 16-bit up/down resettable binary counter (one per function block) tested at v cc = v ccio = 1.9v. 2. see quality and reliability section of the coolrunner-ii family data sheet.
xc2c32a coolrunner-ii cpld 4 www.xilinx.com ds310 (v1.1) august 30, 2004 1-800-255-7778 advance product specification r lvcmos 3.3v and lvttl 3.3v dc voltage specifications lvcmos 2.5v dc voltage specifications lvcmos 1.8v dc voltage specifications 1.5v dc voltage specifications (1) symbol parameter test conditions min. max. units v ccio input source voltage 3.0 3.6 v v ih high level input voltage 2 3.9 v v il low level input voltage ?0.3 0.8 v v oh high level output voltage i oh = ?8 ma, v ccio = 3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 3v - 0.4 v i ol = 0.1 ma, v ccio = 3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 2.3 2.7 v v ih high level input voltage 1.7 3.9 v v il low level input voltage ?0.3 0.7 v v oh high level output voltage i oh = ?8 ma, v ccio = 2.3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 2.3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 2.3v - 0.4 v i ol = 0.1ma, v ccio = 2.3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 1.7 1.9 v v ih high level input voltage 0.65 x v ccio 3.9 v v il low level input voltage ?0.3 0.35 x v ccio v v oh high level output voltage i oh = ?8 ma, v ccio = 1.7v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.7v v ccio ? 0.2 - v v ol low level output voltage i ol = 8 ma, v ccio = 1.7v - 0.45 v i ol = 0.1 ma, v ccio = 1.7v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 1.4 1.6 v v t+ input hysteresis threshold voltage 0.5 x v ccio 0.8 x v ccio v v t- 0.2 x v ccio 0.5 x v ccio v v oh high level output voltage i oh = ?8 ma, v ccio = 1.4v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.4v v ccio ? 0.2 - v v ol low level output voltage i ol = 8 ma, v ccio = 1.4v - 0.4 v i ol = 0.1 ma, v ccio = 1.4v - 0.2 v notes: 1. hysteresis used on 1.5v inputs.
xc2c32a coolrunner-ii cpld ds310 (v1.1) august 30, 2004 www.xilinx.com 5 advance product specification 1-800-255-7778 r schmitt trigger input dc voltage specifications ac electrical characteristics over recommended operating conditions symbol parameter test conditions min. max. units v ccio input source voltage 1.4 3.9 v v t+ input hysteresis threshold voltage 0.5 x v ccio 0.8 x v ccio v v t- 0.2 x v ccio 0.5 x v ccio v symbol parameter -3 -4 -6 units min. max. min. max. min. max . t pd1 propagation delay single p-term - 2.8 - 3.8 - 5.5 ns t pd2 propagation delay or array - 3.0 - 4.0 - 6.0 ns t sud direct input register clock setup time 1.5 - 1.7 - 2.2 - ns t su1 setup time fast (single p-term) 1.5 - 1.9 - 2.6 - ns t su2 setup time (or array) 1.7 - 2.1 - 3.1 - ns t hd direct input register hold time 0.0 - 0.0 - 0.0 - ns t h p-term hold time 0.0 - 0.0 - 0.0 - ns t co clock to output - 2.8 - 3.7 - 4.7 ns f toggle (1) internal toggle rate - 500 - 450 - 300 mhz f system1 (2) maximum system frequency - 417 - 323 - 200 mhz f system2 (2) maximum system frequency - 385 - 303 - 182 mhz f ext1 (3) maximum external frequency - 233 - 179 - 137 mhz f ext2 (3) maximum external frequency - 222 - 172 - 128 mhz t psud direct input register p-term clock setup time 0.6 - 0.4 - 0.9 - ns t psu1 p-term clock setup time (single p-term) 0.6 - 0.6 - 1.3 - ns t psu2 p-term clock setup time (or array) 0.8 - 0.8 - 1.8 - ns t phd direct input register p-term clock hold time 0.9 - 1.5 - 1.6 - ns t ph p-term clock hold 0.9 - 1.3 - 1.2 - ns t pco p-term clock to output - 3.7 - 5.0 - 6.0 ns t oe /t od global oe to output enable/disable - 4.0 - 4.2 - 5.5 ns t poe /t pod p-term oe to output enable/disable - 5.3 - 5.5 - 6.7 ns t moe /t mod macrocell driven oe to output enable/disable - 4.8 - 5.0 - 6.9 ns t pao p-term set/reset to output valid - 4.9 - 5.5 - 6.8 ns t ao global set/reset to output valid - 4.0 - 4.5 - 5.5 ns t suec register clock enable setup time 1.8 - 2.0 - 3.0 - ns t hec register clock enable hold time 0.0 - 0.0 - 0.0 - ns t cw global clock pulse width high or low 0.9 - 1.4 - 2.2 - ns t pcw p-term pulse width high or low 3.0 - 4.0 - 6.0 - ns t config (4) configuration time - 50 - 50 - 50 s notes: 1. f toggle is the maximum clock frequency to which a t-flip flop can reliably toggle (see the coolrunner-ii family data sheet). 2. f system1 (1/t cycle ) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per macrocell while f system2 is through the or array . 3. f ext1 (1/t su1 +t co ) is the maximum external frequency using one p-term while f ext2 is through the or array . 4. typical configuration current during t config is 500 a.
xc2c32a coolrunner-ii cpld 6 www.xilinx.com ds310 (v1.1) august 30, 2004 1-800-255-7778 advance product specification r internal timing parameters symbol parameter (1) -3 -4 -6 units min. max. min. max. min. max. buffer delays t in input buffer delay - 0.8 - 1.3 - 1.7 ns t din direct register input delay - 1.2 - 1.5 - 2.4 ns t gck global clock buffer delay - 1.2 - 1.3 - 2.0 ns t gsr global set/reset buffer delay - 1.2 - 1.6 - 2.0 ns t gts global 3-state buffer delay - 0.8 - 1.3 - 2.1 ns t out output buffer delay - 1.4 - 1.8 - 2.0 ns t en output buffer enable/disable delay - 3.2 - 2.9 - 3.4 ns p-term delays t ct control term delay - 1.3 - 1.3 - 1.6 ns t logi1 single p-term delay adder - 0.4 - 0.4 - 1.1 ns t logi2 multiple p-term delay adder - 0.2 - 0.2 - 0.5 ns macrocell delay t pdi input to output valid - 0.2 - 0.3 - 0.7 ns t ldi setup before clock (transparent latch) - 1.0 - 1.5 - 2.5 ns t sui setup before clock 1.5 - 1.5 - 1.8 - ns t hi hold after clock 0.0 - 0.0 - 0.0 - ns t ecsu enable clock setup time 0.9 - 0.7 - 1.7 - ns t echo enable clock hold time 0.0 - 0.0 - 0.0 - ns t coi clock to output valid - 0.2 - 0.6 - 0.7 ns t aoi set/reset to output valid - 1.4 - 1.1 - 1.5 ns feedback delays t f feedback delay - 0.3 - 0.6 - 1.4 ns t oem macrocell to global oe delay - 0.2 - 0.2 - 0.8 ns i/o standard time adder delays 1.5v i/o t hys15 hysteresis input adder - 2.5 - 3.0 - 4.0 ns t out15 output adder - 0.5 - 0.8 - 1.0 ns t slew15 output slew rate adder - 3.0 - 4.0 - 5.0 ns i/o standard time adder delays 1.8v cmos t hys18 hysteresis input adder - 2.0 - 3.0 - 4.0 ns t out18 output adder - 0.0 - 0.0 - 0.0 ns t slew output slew rate adder - 3.0 - 4.0 - 5.0 ns
xc2c32a coolrunner-ii cpld ds310 (v1.1) august 30, 2004 www.xilinx.com 7 advance product specification 1-800-255-7778 r switching characteristics ac test circuit i/o standard time adder delays 2.5v cmos t in25 standard input adder - 0.7 - 0.8 - 1.0 ns t hys25 hysteresis input adder - 2.5 - 3.0 - 4.0 ns t out25 output adder - 0.8 - 1.0 - 2.0 ns t slew25 output slew rate adder - 4.0 - 5.0 - 7.0 ns i/o standard time adder delays 3.3v cmos/ttl t in33 standard input adder - 0.7 - 0.8 - 1.0 ns t hys33 hysteresis input adder - 2.5 - 3.0 - 4.0 ns t out33 output adder - 1.2 - 1.5 - 2.5 ns t slew33 output slew rate adder - 4.0 - 5.0 - 7.0 ns notes: 1. 1.5 ns input pin signal rise/fall. internal timing parameters (continued) symbol parameter (1) -3 -4 -6 units min. max. min. max. min. max. figure 2: derating curve for t pd number of outputs switching 12 4 8 16 3.0 4.0 5.0 v cc = v ccio = 1.8v @ 25 o c t pd2 (ns) 5.5 4.5 3.5 ds091_02_112002 figure 3: ac load circuit r 1 v cc c l r 2 device under test output type lvttl33 lvcmos33 lvcmos25 lvcmos18 lvcmos15 c l includes test fixtures and probe capacitance. 1.5 nsec maximum rise/fall times on inputs. r 1 268 ? 275 ? 188 ? 112.5 ? 150 ? r 2 235 ? 275 ? 188 ? 112.5 ? 150 ? c l 35 pf 35 pf 35pf 35pf 35pf ds_act_08_14_0 2 test point
xc2c32a coolrunner-ii cpld 8 www.xilinx.com ds310 (v1.1) august 30, 2004 1-800-255-7778 advance product specification r typical i/o output curves figure 4: typical i/v curve for xc2c32a vo (output volts) xc32_voio_all_040 3 io (output current ma) 0 0 40 10 50 20 30 60 3.0 2.5 2.0 1.5 1.0 .5 3 .5 3.3v 1.5v 1.8v 2.5v iol pin descriptions function block macrocell qfg32 pc44 vq44 cp56 i/o bank 1 1 44 38 f1 bank 2 1 2 43 37 e3 bank 2 1 3 42 36 e1 bank 2 1(gts1)434034d1bank 2 1(gts0)523933c1bank 2 1(gts3) 6 1 38 32 a3 bank 2 1(gts2) 7 32 37 31 a2 bank 2 1(gsr) 8 31 36 30 b1 bank 2 1 9 30 35 29 a1 bank 2 1 10 29 34 28 c4 bank 2 111283327c5bank 2 112242923c8bank 2 113 2822a10bank 2 114232721b10bank 2 115 2620c10bank 2 116 2519e8bank 2 2 1 5 1 39 g1 bank 1 22 240f3bank 1 23 341h1bank 1 24 442g3bank 1 2(gck0) 5 6 5 43 j1 bank 1 2(gck1) 6 7 6 44 k1 bank 1 2(gck2) 7 8 7 1 k2 bank 1
xc2c32a coolrunner-ii cpld ds310 (v1.1) august 30, 2004 www.xilinx.com 9 advance product specification 1-800-255-7778 r xc2c32a global, jtag, power/ground and no connect pins ordering information 28982k3bank 1 291093h3bank 1 210 115k5bank 1 211 126h5bank 1 21213148h8bank 1 213171812k8bank 1 2 141819 13h10bank 1 215192014g10bank 1 216 2216f10bank 1 notes: 1. gts = global output enable, gsr = global set reset, gck = global clock pin type qfg32 pc44 (1) vq44 (1) cp56 (1) tck 16 17 11 k10 tdi 14 15 9 j10 tdo 25 30 24 a6 tms 15 16 10 k9 input only 22 24 18 d10 v aux (jtag supply voltage) 4 41 35 d3 power internal (v cc ) power bank 1 i/o (v ccio1 ) power bank 2 i/o (v ccio2 ) 20 21 15 g8 12 13 7 h6 27 32 26 c6 ground 11, 21, 26 10,23,31 4,17,25 h4, f8, c7 no connects - - k4, k6, k7, h7, e10, a7, a9, d8, a5, a8, a4, c3 total user i/o (includes dual function pins) 21 33 33 33 notes: 1. all packages pin compatible with larger macrocell densities part number pin/ball spacing ja (c/watt) jc (c/watt) package type package body dimensions i/o comm. (c) ind. (i) (1) xc2c32a-3qfg32c 0.5mm 35.5 24.0 quad flat no lead; pb-free 5mm x 5mm 21 c xc2c32a-4qfg32c 0.5mm 35.5 24.0 quad flat no lead; pb-free 5mm x 5mm 21 c xc2c32a-6qfg32c 0.5mm 35.5 24.0 quad flat no lead; pb-free 5mm x 5mm 21 c xc2c32a-3pc44c 1.27mm 55.1 35.3 plastic leaded chip carrier 16.5mm x 16.5mm 33 c xc2c32a-4pc44c 1.27mm 55.1 35.3 plastic leaded chip carrier 16.5mm x 16.5mm 33 c pin descriptions (continued) function block macrocell qfg32 pc44 vq44 cp56 i/o bank
xc2c32a coolrunner-ii cpld 10 www.xilinx.com ds310 (v1.1) august 30, 2004 1-800-255-7778 advance product specification r xc2c32a-6pc44c 1.27mm 55.1 35.3 plastic leaded chip carrier 16.5mm x 16.5mm 33 c xc2c32a-3vq44c 0.8mm 47.7 8.2 very thin quad flat pack 10mm x 10mm 33 c xc2c32a-4vq44c 0.8mm 47.7 8.2 very thin quad flat pack 10mm x 10mm 33 c xc2c32a-6vq44c 0.8mm 47.7 8.2 very thin quad flat pack 10mm x 10mm 33 c xc2c32a-3cp56c 0.5mm 66.0 14.9 chip scale package 6mm x 6mm 33 c xc2c32a-4cp56c 0.5mm 66.0 14.9 chip scale package 6mm x 6mm 33 c xc2c32a-6cp56c 0.5mm 66.0 14.9 chip scale package 6mm x 6mm 33 c xc2c32a-3pcg44c 1.27mm 55.1 35.3 plastic leaded chip carrier; pb-free 16.5mm x 16.5mm 33 c xc2c32a-4pcg44c 1.27mm 55.1 35.3 plastic leaded chip carrier; pb-free 16.5mm x 16.5mm 33 c xc2c32a-6pcg44c 1.27mm 55.1 35.3 plastic leaded chip carrier; pb-free 16.5mm x 16.5mm 33 c xc2c32a-3vqg44c 0.8mm 47.7 8.2 very thin quad flat pack; pb-free 10mm x 10mm 33 c xc2c32a-4vqg44c 0.8mm 47.7 8.2 very thin quad flat pack; pb-free 10mm x 10mm 33 c xc2c32a-6vqg44c 0.8mm 47.7 8.2 very thin quad flat pack; pb-free 10mm x 10mm 33 c xc2c32a-3cpg56c 0.5mm 66.0 14.9 chip scale package; pb-free 6mm x 6mm 33 c XC2C32A-4CPG56C 0.5mm 66.0 14.9 chip scale package; pb-free 6mm x 6mm 33 c xc2c32a-6cpg56c 0.5mm 66.0 14.9 chip scale package; pb-free 6mm x 6mm 33 c xc2c32a-6qfg32i 0.5mm 35.5 24.0 quad flat no lead; pb-free 5mm x 5mm 21 i xc2c32a-6pc44i 1.27mm 55.1 35.3 plastic leaded chip carrier 16.5mm x 16.5mm 33 i xc2c32a-6vq44i 0.8mm 47.7 8.2 very thin quad flat pack 10mm x 10mm 33 i xc2c32a-6cp56i 0.5mm 66.0 14.9 chip scale package 6mm x 6mm 33 i xc2c32a-6pcg44i 1.27mm 55.1 35.3 plastic leaded chip carrier; pb-free 16.5mm x 16.5mm 33 i part number pin/ball spacing ja (c/watt) jc (c/watt) package type package body dimensions i/o comm. (c) ind. (i) (1)
xc2c32a coolrunner-ii cpld ds310 (v1.1) august 30, 2004 www.xilinx.com 11 advance product specification 1-800-255-7778 r device part marking figure 5: sample package with part marking note: due to the small size of chip scale and quad flat no lead packages, the complete ordering part number cannot be included on the package marking. part marking on chip scale and quad flat no lead packages by line are: ? line 1 = x (xilinx logo) then truncated part number ? line 2 = not related to device part number ? line 3 = not related to device part number ? line 4 = package code, speed, operating temperature, three digits not related to device part number. package codes: c3 = cp56, c4 = cpg56, q1 = qfg32. xc2c32a-6vqg44i 0.8mm 47.7 8.2 very thin quad flat pack; pb-free 10mm x 10mm 33 i xc2c32a-6cpg56i 0.5mm 66.0 14.9 chip scale package; pb-free 6mm x 6mm 33 i notes: 1. c = commercial (t a = 0c to +70c); i = industrial (t a = ?40c to +85c) part number pin/ball spacing ja (c/watt) jc (c/watt) package type package body dimensions i/o comm. (c) ind. (i) (1) standard example: xc2c128 device speed grade package type number of pins temperature range -4 tq c 144 pb- free example: xc2c128 tq g 144 c device speed grade package type pb -free number of pins -4 temperature range xc2cxxx tq144 7c device type package speed operating range this line not related to device part number r part marking for non-chip scale package
xc2c32a coolrunner-ii cpld 12 www.xilinx.com ds310 (v1.1) august 30, 2004 1-800-255-7778 advance product specification r figure 6: qfg32 package figure 7: vq44 package figure 8: pc44 package qfg32 top view i/o i/o input gnd vcc i/o i/o i/o i/o(1 ) i/o(3 ) i/o i/o i/o vccio 2 gnd tdo i/o i/o gnd vccio1 i/o tdi tms tck i /o(1) i /o(1) i /o(1) v aux i /o i /o(2) i /o(2) i /o(2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 (1) - global output enable (2) - global clock (3) - global set/reset vq44 top view i/o (1) i/o (1) i/o (1) i/o (3) i/o i/o i/o v ccio2 gnd tdo i/o i/o (2 ) i/o (2 ) i/o i/o i/o i/o i/o i/o i/o v au x i/o (1 ) i/o i/o i/o v cc i/o gnd i i/o i/o i/o i/o i/o (2) i/o i/o gnd i/o i/o v ccio1 i/o tdi tms tck 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 (1) - global output enab le (2) - global clock (3) - global set/reset pc44 top view i/o (1) i/o (1) i/o (1) i/o (3) i/o i/o i/o v ccio2 gnd tdo i/o i/o (2 ) i/o (2 ) i/o i/o i/o i/o i/o i/o i/o v au x i/o (1 ) i/o i/o i/o v cc i/o gnd i i/o i/o i/o i/o i/o (2) i/o i/o gnd i/o i/o v ccio1 i/o tdi tms tck 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 6 5 4 3 2 1 44 43 42 41 40 (1) - global output enab le (2) - global clock (3) - global set/reset
xc2c32a coolrunner-ii cpld ds310 (v1.1) august 30, 2004 www.xilinx.com 13 advance product specification 1-800-255-7778 r additional information coolrunner-ii datasheets and application notes online store device package drawings revision history the following table shows the revision history for this document. figure 9: cp56 package cp56 bottom view i/o (2) i/o (2) i/o nc i/o nc nc i/o tms tck i/o (2) tdi i/o i/o gnd i/o v cc io1 nc i/o i/o i/o i/o v cc i/o i/o i/o gnd i/o i/o i/o i/o nc i/o (1) v aux nc i i/o (1) nc i/o i/o v cc io2 gnd i/o i/o i/o (3) i/o i/o i/o (1) i/o (1) nc nc tdo nc nc nc i/o k j h g f e d c b a 1 2 3 4 5 6 7 8 9 1 0 (1) - global output enable (2) - global clock (3) - global set/reset date version revision 6/15/04 1.0 initial xilinx release. 8/30/04 1.1 pb-free documentation

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